26 Jun 09 Modeling and Verification Using UML Statecharts: A Working Guide to Reactive System Design, Runtime Monitoring and Execution-based Model Checking
Modeling and Verification Using UML Statecharts
Product Description
As systems being developed by industry and government grow larger and more complex, the need for superior specification and verification approaches and tools becomes increasingly vital. The developer and customer must have complete confidence that the design produced is correct, and that it meets forma development and verification standards. In this text, UML expert author Dr. Doron Drusinsky compiles all the latest information on the application of UML (Universal Modeling Language) statecharts, temporal logic, automata, and other advanced tools for run-time monitoring and verification. This is the first book that deals specifically with UML verification techniques. This important information is introduced within the context of real-life examples and solutions, particularly focusing on national defense applications. A practical text, as opposed to a high-level theoretical one, it emphasizes getting the system developer up-to-speed on using the tools necessary for daily practice.
· A practical, tutorial-style text (other books on this topic discuss the tools and formalisms only theoretically)
· Includes an unclassified case study example from the U.S. Missile Defense project
·Accompanying CD-ROM includes source code and re-useable statechart templates
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Related eBooks:
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- Practical UML Statecharts in C/C++, Second Edition: Event-Driven Programming for Embedded Systems (Paperback)
- Hardware Verification with C++: A Practitioners Handbook
- Next Generation Design and Verification Methodologies for Distributed Embedded Control Systems
- SimplyMax – Modeling Cartoon Rat Model
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- Scalable Hardware Verification with Symbolic Simulation
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